1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more specifically to dual port memory devices.
2. Description of the Prior Art
Computer systems utilize cache memories to enhance system performance. A data cache contains the cached data, and a cache tag memory contains the addresses of data stored in the cache. A processor, when making a memory access, accesses the desired memory location through the cache. If the desired location is already in the cache, access is complete. If it is not, the memory location is fetched from main system memory and loaded into the cache.
The speed of the integrated circuit devices used in the cache are important. The cache tag memory must provide a hit or a miss signal for every memory access by the processor. If the cache tag memory is slightly slow, the performance of the entire system suffers.
As is known in the art, one technique to improve the operating speed of integrated circuit devices is to reduce or balance stray capacitances. Memories have relatively long bit lines which contribute significantly to such capacitances. Good device design can help minimize such capacitances, but the nature of a memory device causes inevitable problems. Therefore, balancing of bit lines in a memory device layout is important.
No successful design has previously been done for a dual port cache tag memory device. In such a device, the capacitances for two sets of bit lines must be considered. In addition to stray capacitances, coupling capacitances between bit lines for the two ports can adversely impact device performance. In a dual port cache tag memory, in which speed is important, the extra problems caused by the extra bit lines can be significant.
It would therefore be desireable to provide a layout and design for a dual port memory device which minimized problems caused by stray and cross coupling capacitances. Such design preferably provides significantly improved performance without adding undue complication to the overall device design. It is desirable that the dual port memory device design is suitable for use in cache tag memory integrated circuit devices.